2010

• 

  Andrea Acquaviva, Andrea Calimera, Alberto Macii, Massimo Poncino, Enrico Macii, Matteo Giaconia, and Claudio Parrella. An integrated thermal estimation framework for industrial embedded platforms. In GLSVLSI '10: Proceedings of the 20th symposium on Great lakes symposium on VLSI, pages 293–298, New York, NY, USA, 2010. ACM. ISBN 978-1-4503-0012-4.

  Next generation industrial embedded platforms require the development of complex power and thermal management solutions. Indeed, an increasingly fine and intrusive thermal control is required because of temperature impact on leakage and reliability. To be effective, the implementation of these policies involves decisions that must be taken during various phases along the design process, to enable the development of architectural level countermeasures and the required hardware knobs, such as power modes, power supply regulation granularity and the number of on-chip temperature sensors. As a consequence, a framework allowing thermal estimation exploiting design-time information is desirable. In this paper we propose a solution on this direction, by presenting an integrated estimation environment for the evaluation of chip temperature profiles. It exploits heterogeneous power information available during the design phase. Power information is used to drive a thermal simulation engine capable of temperature feedback for the emulation of on-chip sensors. The framework has been demonstrated on an industrial case study, namely the ST SPEAr1300 embedded platform. Experimental results show how the proposed framework can be used to evaluate the temperature of a single component in isolation and also the effect on the temperature profile of the interactions among chip components depending on their power states. Finally we demonstrate the effect of temperature feedback on leakage power consumption.

  @inproceedings{1785550,
  

  author       = {Acquaviva, Andrea and Calimera, Andrea and Macii, Alberto and Poncino, Massimo and Macii, Enrico and Giaconia, Matteo and Parrella, Claudio},

  title        = {An integrated thermal estimation framework for industrial embedded platforms},

  booktitle    = {GLSVLSI '10: Proceedings of the 20th symposium on Great lakes symposium on VLSI},

  pages        = {293--298},

  year         = {2010},

  publisher    = {ACM},

  address      = {New York, NY, USA},

  isbn         = {978-1-4503-0012-4},

  }
• 

  D. Alders. Green technologies for economic growth in europe. CD-ROM, March 2010. Embedded World 2010 - ARTEMIS session.

  The goal of SCALOPES is to enable an industrially sustainable path for the evolution of low-power multi-core computing platforms for application domains with strategic value for European competitiveness. The technical innovations are driven by and proven for 4 different application domains: communication infrastructure, surveillance systems, smart mobile terminals and stationary video systems. Headed by NXP Semiconductors in the Netherlands, SCALOPES has 39 partners from 12 countries, including leading European semiconductor companies, small and medium-sized enterprises (SMEs), research institutes and universities.

  @misc{alders_2010,
  

  author       = {Alders, D.},

  title        = {Green technologies for economic growth in Europe},

  month        = mar,

  year         = {2010},

  howpublished = {CD-ROM},

  note         = {Embedded World 2010 - ARTEMIS session},

  }

• Heřmánek Antonin, Michel Kuneš, and Milan Tichý. Reducing Power Consumption of an Embedded DSP Platform through the Clock-Gating Technique. In Proceedings 20th International Conference on Field Programmable Logic and Applications (FPL), 2010.

  The paper describes application of the clock-gating techniques, often used in ASIC designs, to the field of FPGA based systems. The clock-gating techniques are used to reduce the total power of the system. To achieve this, we reduce clock power consumption of the system by switching-off the clock signal for the parts of system that are not used. The system presented in this paper is based on the main processor, extended with several reconfigurable accelerators. These accelerators extend the processor capabilities by several vector operations and can be reprogrammed in run-time. Clock gating, in our design, is used to switch the accelerators off when not used. As the accelerators can represent a major part of the system size, switching them off can significantly reduce the power consumption. We also propose the method for estimation of the reduction of power consumption that can be achieved using the clock-gating technique.

  @inproceedings{Antonin2010,
  

  author       = {Antonin, He\v{r}m\'{a}nek and Kune\v{s}, Michel and Tich\'{y}, Milan},

  title        = {{R}educing {P}ower {C}onsumption of an {E}mbedded {DSP} {P}latform through the {C}lock-{G}ating {T}echnique},

  booktitle    = {Proceedings 20th International Conference on Field Programmable Logic and Applications (FPL)},

  year         = {2010},

  }

• Jan Kloub, Petr Honzik, and Martin Daněk. Reconfigurable Hardware Objects for Image Processing on FPGAs. In Proceedings of the 13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems DDECS 2010, pages 121–122, 2010. ISBN 978-1-4244-6610-8.

  Embedded systems are getting more complex and that is why the high level of abstraction is required the during development process. High abstraction methods simplify implementation of complex computation systems and shorten the time to market. This paper presents an implementation of a graphic computing element (GCE) which can be used as a runtime parametrized building block in image processing applications in FPGAs. In terms of the object oriented model, the GCE encapsulates its internal data representation and rules for their manipulation. Several basic image processing operations were implemented (Sobel edge detection, Gauss, mean, etc. filtering). These operations are called as GCE methods. Because of high spatial dependency of image data in image processing, an efficient image data reuse method was implemented.

  @inproceedings{Kloub2010,
  

  author       = {Kloub, Jan and Honzik, Petr and Dan\v{e}k, Martin},

  title        = {{R}econfigurable {H}ardware {O}bjects for {I}mage {P}rocessing on {FPGA}s},

  booktitle    = {Proceedings of the 13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems DDECS 2010},

  pages        = {121--122},

  year         = {2010},

  isbn         = {978-1-4244-6610-8},

  }

• István Moldován, Tuan Anh Trinh, Sándor Plósz, and Andreas Foglar. Design and Implementation of a Practical Smart Home System Based on DECT Technology. In E-Energy 2010, October 2010.

  Energy management is important not only for the homes, but also for the energy providers. With the ever-increasing broadbandpenetration it becomes possible the information exchange between the energy provider and customer, and a smart home management system. In this paper, we present a practical smart home system that serves as platform for efficient metering and communication within the household. The interconnection of the home appliances and the home network is realized by light-weight, feature-rich and cost-effective DECT technology (Digital Enhanced Cordless Tele-communications). Furthermore, we provide a concept of integration of the smart home system within the smart energy grid. A model is presented which served as the basis of the design and prototype realization of components of the system including an energy management device (EMD), DECT communication interfaces based on state-of-the-art technology. Finally, we present our prototype system for the concept.

  @inproceedings{MoldovanEEnergy2010,
  

  author       = {Moldov\'{a}n, Istv\'{a}n and Anh Trinh, Tuan and Pl\'{o}sz, S\'{a}ndor and Foglar, Andreas},

  title        = {{D}esign and {I}mplementation of a {P}ractical {S}mart {H}ome {S}ystem {B}ased on {DECT} {T}echnology},

  booktitle    = {E-Energy 2010},

  month        = oct,

  year         = {2010},

  }

• István Moldován, Dániel Horváth, Imre Bertalan, and Tuan Anh Trinh. An Energy-Efficient FPGA-Based Packet Processing Framework. In EUNICE 2010, June 2010.

  Modern packet processing hardware (e.g. IPv6-supported routers) demands high processing power, while it also should be power-efficient. In this paper we present an architecture for high-speed packet processing with a hierarchical chip-level power management that minimizes the energy consumption of the system. In particular, we present a modeling framework that provides an easy way to create new networking applications on an FPGA based board. The development environment consists of a modeling environment, where the new application is modeled in SystemC. Furthermore, our power management is modeled and tested against different traffic loads through extensive simulation analysis. Our results show that our proposed solution can help to reduce the energy consumption significantly in a wide range of traffic scenarios

  @inproceedings{MoldovanEunice2010,
  

  author       = {Moldov\'{a}n, Istv\'{a}n and Horv\'{a}th, D\'{a}niel and Bertalan, Imre and Anh Trinh, Tuan},

  title        = {{A}n {E}nergy-{E}fficient {FPGA}-{B}ased {P}acket {P}rocessing {F}ramework},

  booktitle    = {EUNICE 2010},

  month        = jun,

  year         = {2010},

  }

• István Moldován, Pál Varga, Sándor Plósz, and Dániel Horváth. A low Power, Programmable Networking Platform and Development Toolchain. In NEMA 2010, October 2010.

  As the 10 Gigabit Ethernet interfaces are more and more commonly used in the networks, the demand for different management functions at this speed urges the development of platforms capable of handling such traffic. We present an FPGA based programmable platform, capable of real-time processing, filtering 10Gbps traffic or even forwarding it towards the more than 16 onboard SFPs. The design is modular, programmable in both hardware (firmware) and software, aiming low power consumption and also low cost. The full potential of the hardware can only be exploited with an easy-to-use development environment, with simple design customization and support for creating new applications. Therefore a development toolchain is presented including a modeling framework that provides an easy way to create new networking applications on the board. The development toolchain consists of a modeling environment, where the new application is modeled in SystemC, and also eases the development of the hardware description code.

  @inproceedings{MoldavanNema2010,
  

  author       = {Moldov\'{a}n, Istv\'{a}n and Varga, P\'{a}l and Pl\'{o}sz, S\'{a}ndor and Horv\'{a}th, D\'{a}niel},

  title        = {{A} Low {P}ower, {P}rogrammable {N}etworking {P}latform and {D}evelopment {T}oolchain},

  booktitle    = {NEMA 2010},

  month        = oct,

  year         = {2010},

  }

• István Moldován, Pál Varga, Sándor Plósz, and László Kántor. Dependability of a network monitoring hardware. In Depend 2010, Venice/Mestre, Italy, July 17th-22th 2010. The Third International Conference on Dependability.

  System dependability plays an important role in the realization of computer communication infrastructures and the everyday operations and maintenance of computer networks. Increased redundancy is used as a common practice to improve dependability, however in some cases duplication of a networking equipment is not desirable due to high cost or increased system complexity as a result of handling potentially duplicated data. In such cases a single point of failure exists. In this paper we first present a highly dependable networking hardware architecture and demonstrate its application in a monitoring example then we provide a detailed dependability analysis for the hardware used in monitoring application.

  @inproceedings{MoldovanDepend2010,
  

  author       = {Moldov\'{a}n, Istv\'{a}n and Varga, P\'{a}l and Pl\'{o}sz, S\'{a}ndor and K\'{a}ntor, L\'{a}szl\'{o}},

  title        = {Dependability of a Network Monitoring Hardware},

  booktitle    = {Depend 2010},

  month        = {July 17th-22th},

  year         = {2010},

  organization = {The Third International Conference on Dependability},

  address      = {Venice/Mestre, Italy},

  }

• T. Sassolas, N. Ventroux, and G. Blanc. A Power-Aware Online Scheduling Algorithm for Streaming Applications in Embedded MPSoC. In IEEE International Workshop on Power and Timing Modeling, optimization and Simulation (PATMOS), Grenoble, France, September 2010.

  As application complexity grows, embedded systems move to multiprocessor architectures to cope with the computation needs. The issue for multiprocessor architectures is to optimize the processing re- sources usage and power consumption to reach a higher energy efficiency. These optimizations are handled by scheduling techniques. To tackle this issue we propose a global online scheduling algorithm for streaming appli- cations. It takes into account data dependencies between pipeline tasks to optimize processor usage and reduce power consumption through the use of DPM and DVFS modes. An implementation of the algorithm on a virtual platform, executing a WCDMA application, demonstrates up to 45% power consumption gain while guaranteeing regular data through- put.

  @inproceedings{Sassolas2010,
  

  author       = {T. Sassolas and N. Ventroux and G. Blanc},

  title        = {{A} {P}ower-{A}ware {O}nline {S}cheduling {A}lgorithm for {S}treaming {A}pplications in {E}mbedded {MPSoC}},

  booktitle    = {{IEEE} {I}nternational {W}orkshop on {P}ower and {T}iming {M}odeling, optimization and {S}imulation ({PATMOS})},

  month        = sep,

  year         = {2010},

  address      = {Grenoble, France},

  }

• Tomáš Urban, Ondřej Šubrt, and Pravoslav Martinek. Versatile Sub-BandGap Reference IP core. In Proceedings of the 13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems DDECS 2010, pages 393–398, 2010. ISBN 978-1-4244-6610-8.

  A step-by-step design procedure of sub-bandgap voltage reference (BGR) is proposed. The procedure shows on example structure main design steps of crucial parameters verified later by a simulation. The block is meant to be fabricated in 0.35µm CMOS process with analog options. The main features of the concept are the sub-bandgap output voltage of 0.7V, low supply voltage from 1.3V, low power consumption under 10µm, versatility, high working temperature range from -50 to 95 ℃. The versatility of the block is supported by a temperature slope trimming, extended start-up and self testing. The IP block is compact, ready to adjust, layout and integrate. The features of the design also allow the in-circuit tuning. This example circuit shows the use of the design algorithm including the optimization suggestions which lead to a complex design.

  @inproceedings{Urban2010,
  

  author       = {Urban, Tom\'{a}\v{s} and \v{S}ubrt , Ond\v{r}ej and Martinek, Pravoslav},

  title        = {{V}ersatile {S}ub-{B}and{G}ap {R}eference {IP} Core},

  booktitle    = {Proceedings of the 13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems DDECS 2010},

  pages        = {393--398},

  year         = {2010},

  isbn         = {978-1-4244-6610-8},

  }

• N. Ventroux, T. Sassolas, R. David, G. Blanc, A. Guerre, and C. Bechara. SESAM Extension For Fast MPSoC Architectural Exploration And Dynamic Streaming Application. In IEEE/IFIP International Conference on VLSI and System-on-Chip (VLSI-SoC), 2010.

  Future systems will have to support multiple and concurrent dynamic compute-intensive applications, while respecting real-time and energy consumption constraints. To overcome these computation needs, only multithreaded approaches are possible. Thus, the support of a streaming execution model is very important for dataflow applications. However, with dynamic applications, each execution stage is prone to execution time variations. The sizing of these highly complex MPSoC architectures becomes difficult. In such a context, flexible and accurate simulators become a necessity for exploring the vast design space solution. In this paper, we use the SESAM environment to ease the architectural exploration of asymmetric MPSoCs for dynamic streaming application processing. This paper focuses on the new programming and execution model supported by the simulator, and studies performances obtained with a WCDMA encoder/decoder application implemented on a complete MPSoC platform.

  @inproceedings{Ventroux2010,
  

  author       = {N. Ventroux and T. Sassolas and R. David and G. Blanc and A. Guerre and C. Bechara},

  title        = {{SESAM} {E}xtension {F}or {F}ast {MPSoC} {A}rchitectural {E}xploration {A}nd {D}ynamic {S}treaming {A}pplication},

  booktitle    = {IEEE/IFIP International Conference on VLSI and System-on-Chip (VLSI-SoC)},

  pages        = {},

  year         = {2010},

  }

2009

• G. Beltrame, L. Fossati, and D. Sciuto. ReSP: A non-intrusive transaction-level reflective MPSoC simulation. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 28, 2009. Politecnico di Milano.

  This paper presents reflective simulation platform (ReSP), a transaction-level multiprocessor simulation platform based on the integration of SystemC and Python. ReSP exploits the concept of reflection, enabling the integration of SystemC components without source-code modifications and providing full observability of their internal state. ReSP offers fine-grained simulation control and supports the evaluation of different hardware/software configurations of a given application, enabling complete design space exploration. ReSP allows the evaluation of real-time applications on high-level hardware models since it provides the transparent emulation of POSIX-compliant real-time operating systems (RTOS) primitives. A number of experiments have been performed to validate ReSP and its capabilities, using a set of single- and multithreaded benchmarks, with both POSIX Threads (PThreads) and OpenMP programming styles. These experiments confirm that reflection introduces negligible ( <1%) overhead when comparing ReSP to plain SystemC simulation. The results also show that ReSP can be successfully used to analyze and explore concurrent and reconfigurable applications even at very early development stages. In fact, the average error introduced by ReSP's RTOS emulation is below 6.6 plusmn 5% w.r.t. the same RTOS running on an instruction set simulator, while simulation speed increases by a factor of ten. Owing to the integration with a scripted language, simulation management is simplified, and experimental setup effort is considerably reduced.

  @article{beltrame_2009,
  

  author       = {Beltrame, G. and Fossati, L. and Sciuto, D.},

  title        = {{ReSP}: A non-intrusive Transaction-Level Reflective {MPSoC} Simulation},

  journal      = {IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems},

  volume       = {28},

  year         = {2009},

  note         = {Politecnico di Milano},

  }

• Gert Goossens and Erik Brockmeyer. The ASIP Advantage - How to Design High-Performance, Low-Power, Software-Programmable Systems-on-Chip. Presentation by Target Compiler Technologies, May 2009. ChipEx, Tel Aviv (Israel).

  @misc{gert_israel_2009,
  

  author       = {Gert Goossens and Erik Brockmeyer},

  title        = {The {ASIP} {A}dvantage - {H}ow to {D}esign {H}igh-{P}erformance, {L}ow-{P}ower, {S}oftware-{P}rogrammable {S}ystems-on-{C}hip},

  journal      = {4th {M}ulticore {E}xpo},

  month        = may,

  year         = {2009},

  howpublished = {Presentation by Target Compiler Technologies},

  note         = {ChipEx, Tel Aviv (Israel)},

  }

• Gert Goossens and Erik Brockmeyer. Design of a Multicore JPEG Encoder Engine Using ASIP Design Tools. Presentation on application-specific processor design tools, using a JPEG encoding example, March 17-19 2009. Santa Clara, CA, USA.

  @misc{gert_santa_clara_2009,
  

  author       = {Gert Goossens and Erik Brockmeyer},

  title        = {Design of a {M}ulticore {JPEG} {E}ncoder {E}ngine {U}sing {ASIP} {D}esign {T}ools},

  journal      = {4th {M}ulticore {E}xpo},

  month        = {March 17-19},

  year         = {2009},

  howpublished = {Presentation on application-specific processor design tools, using a JPEG encoding example},

  note         = {Santa Clara, CA, USA},

  }

• Michele Magno, Davide Brunelli, and Luca Benini. Detection of abandoned/removed objects with a video sensor node aided by IR Sensor. POSTER, February 11th-13th 2009. EWSN 2009, 6th European Conference on Wireless Sensor Networks, Cork, Ireland.

  The interest in low-cost and small size video surveillance systems able to collaborate in a network has been increasing over the last years. Thanks to the progress in low-power design, research has greatly reduced the size and the power consumption of such distributed embedded systems providing flexibility, quick deployment and allowing the implementation of effective vision algorithms performing image processing directly on the embedded node. In this paper we present a multi-modal video sensor node designed for low-power and low-cost video surveillance able to detect changes in the environment. The system is equipped with a CMOS video camera and Pyroelectric InfraRed (PIR) sensors exploited to reduce remarkably the power consumption of the system in absence of events. We analyze different configurations and characterize the system in terms of runtime execution and power consumption.

  @misc{michele_ewsn_2009,
  

  author       = {Magno, Michele and Brunelli, Davide and Benini, Luca},

  title        = {{D}etection of abandoned/removed objects with a video sensor node aided by {IR} {S}ensor},

  month        = {February 11th-13th},

  year         = {2009},

  howpublished = {POSTER},

  note         = {{EWSN} 2009, 6th European Conference on Wireless Sensor Networks, Cork, Ireland},

  }

• Michele Magno, Davide Brunelli, Lothar Thiele, and Luca Benini. Adaptive Power Control for Solar Harvesting: Multimodal Wireless Smart Camera. In ICDSC, Como (Italy), 30 August - 2 September 2009. Third ACM/IEEE International Conference on Distributed Smart Cameras.

  Energy efficiency for wireless smart camera networks is one of the major efforts in distributed monitoring and surveillance community. If video cameras are equipped with circuits that receive and convert energy from regenerative sources such as solar cells, an effective power management becomes essential for the design of small sized and perpetually powered devices, which can be deployed unattended for years and feature smart vision applications. In this paper we present a simple but optimal power management tailored for multi-modal video sensor nodes and based on model predictive controller (MPC). The system is designed for low-power and low-cost video surveillance and exploits small solar cells for battery recharging and Pyroelectric InfraRed (PIR) sensors to provide low-power monitoring when the camera is not needed. The aim of this work is to show how an adaptive controller helps the system to improve the performances outperforming naive power management policies. Simulation results and measurements on the video sensor node demonstrate the efficiency of our approach.

  @inproceedings{michele_icdsc_2009,
  

  author       = {Magno, Michele and Brunelli, Davide and Thiele, Lothar and Benini, Luca},

  title        = {{A}daptive {P}ower {C}ontrol for {S}olar {H}arvesting: {M}ultimodal {W}ireless {S}mart {C}amera},

  booktitle    = {{ICDSC}},

  month        = {30 August - 2 September},

  year         = {2009},

  publisher    = {Third ACM/IEEE International Conference on Distributed Smart Cameras},

  address      = {Como (Italy)},

  }

• Michele Magno, Federico Tombari, Davide Brunelli, Luigi Di Stefano, and Luca Benini. Multimodal abandoned/removed object detection for low power video surveillance systems. In AVSS, Genoa, Italy, September 2-4 2009. 6th IEEE International Conference on Advanced Video and Signal Based Surveillance.

  Low-cost and low-power video surveillance systems based on networks of wireless video sensors will enter soon the marketplace with the promise of flexibility, quick deployment and providing accurate and real-time visual data. Energy autonomy and efficiency of the implemented algorithms are undoubtedly the primary design challenges to be addressed on systems subject to low computational capabilities and memory constraints. In this paper we present a low-power video sensor node designed for low- cost video surveillance which is able to detect aban- doned and removed objects. The system exploits multi- modal sensor integration which saves on-board power consumption. In particular a Pyroelectric InfraRed (PIR) sensor is exploited to optimize the use of the camera, grabbing images only when required in order to obtain the maximum efficiency from event recognition. Our fixed- point ARM-based approach is characterized in terms of runtime execution and power consumption, while efficiency is demonstrated by experimental results and compared with floating point implementations.

  @inproceedings{michele_avss,
  

  author       = {Magno, Michele and Tombari, Federico and Brunelli, Davide and Luigi Di Stefano and Benini, Luca},

  title        = {Multimodal abandoned/removed object detection for low power video surveillance systems},

  booktitle    = {{AVSS}},

  month        = {September 2-4},

  year         = {2009},

  publisher    = {6th IEEE International Conference on Advanced Video and Signal Based Surveillance},

  address      = {Genoa, Italy},

  }
• 

  Sjoerd Meijer, Hristo Nikolov, and Todor Stefanov. On compile-time evaluation of process partitioning transformations for Kahn process networks. In CODES+ISSS '09: Proceedings of the 7th IEEE/ACM international conference on Hardware/software codesign and system synthesis, pages 31–40, New York, NY, USA, 2009. ACM. ISBN 978-1-60558-628-1.

  Kahn Process Networks is an appealing model of computation for programming and mapping applications onto multi-processor platforms. Autonomous processes communicate through unbounded FIFO channels in absence of a global scheduler. We derive Kahn process networks from sequential applications using the pn compiler, but the derived networks do not necessarily meet the performance requirements. Process partitioning transformations can achieve a more balanced network improving the performance results significantly. There are a number of process partitioning transformations that can be used, but no hints are given to the designer which transformation should be applied to minimize, for example, the execution time. Therefore, we investigate a compile-time approach for selecting the best transformation candidate and show results on a Xilinx Virtex 2 FPGA and the Cell BE processor.

  @inproceedings{1629441,
  

  author       = {Meijer, Sjoerd and Nikolov, Hristo and Stefanov, Todor},

  title        = {On compile-time evaluation of process partitioning transformations for {K}ahn process networks},

  booktitle    = {CODES+ISSS '09: Proceedings of the 7th IEEE/ACM international conference on Hardware/software codesign and system synthesis},

  pages        = {31--40},

  year         = {2009},

  publisher    = {ACM},

  address      = {New York, NY, USA},

  isbn         = {978-1-60558-628-1},

  }
• 

  Anca Molnos and Kees Goossens. Conservative dynamic energy management for real-time dataflow applications mapped on multiple processors. Digital Systems Design, Euromicro Symposium on, 0:409–418, 2009.

  Voltage-frequency scaling (VFS) trades a linear processor slowdown for a potentially quadratic reduction in energy consumption. Complex dependencies may exist between different tasks of an application. The impact of VFS on the endto-end application performance is difficult to predict, especially when these tasks are mapped on multiple processors that are scaled independently. This is a problem for real-time (RT) applications that require guaranteed end-to-end performance. In this paper we first classify the slack existing in RT applications consisting of multiple dependent tasks mapped on multiple processors independently using VFS, resulting in static, work, and share slack. Then we concentrate on work and share slack as they can only be detected at run time, thus their conservative use is challenging. We propose SlackOS, a dynamic, dependency-aware, task scheduling that conservatively scales the voltage and frequency of each processor, to respect RT deadlines. When applied to a H.264 application, our method delivers 22% to 33% energy reduction, compared to dynamic RT scheduling that is not energy aware.

  @article{10.1109/DSD.2009.229,
  

  author       = {Molnos, Anca and Goossens, Kees},

  title        = {Conservative Dynamic Energy Management for Real-Time Dataflow Applications Mapped on Multiple Processors},

  journal      = {Digital Systems Design, Euromicro Symposium on},

  volume       = {0},

  pages        = {409-418},

  year         = {2009},

  publisher    = {IEEE Computer Society},

  address      = {Los Alamitos, CA, USA},

  isbn         = {978-0-7695-3782-5},

  }

• Fabrizio Mulas, David Atienza, Andrea Acquaviva, Salvatore Carta, Luca Benini, and Giovanni De Micheli. Thermal Balancing Policy for Multiprocessor Stream Computing Platforms. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 28(12):1870–1882, 2009.

  Die-temperature control to avoid hotspots is increasingly critical in Multiprocessor System-on-Chip (MPSoCs) for stream computing. In this context, thermal balancing policies based on task migration are a promising approach to re-distribute power dissipation and even out temperature gradients. Since stream computing applications require strict quality of service and timing constraints, the real-time performance impact of thermal balancing policies must be carefully evaluated. In this paper we present the design of a lightweight thermal balancing policy, MiGra, which bounds on- chip temperature gradients via task migration. The proposed policy exploits run-time temperature as well as workload information of streaming applications to define suitable run-time thermal migration patterns, which minimize the number of deadline misses. Furthermore, we have experimentally assessed the effectiveness of our thermal balancing policy using a complete Field-Programmable Gate Array (FPGA)-based emulation of an actual 3-core MPSoC streaming platform coupled with a thermal simulator. Our results indicate that MiGra achieves significantly better thermal balancing than state-of-the-art thermal management solutions, while keeping the number of migrations bounded.

  @article{ESL-ARTICLE-2009-010,
  

  author       = {Mulas, Fabrizio and Atienza, David and Acquaviva, Andrea and Carta, Salvatore and Benini, Luca and De Micheli, Giovanni},

  title        = {Thermal {B}alancing {P}olicy for {M}ultiprocessor {S}tream {C}omputing {P}latforms},

  journal      = {{IEEE} {T}ransactions on {C}omputer-{A}ided {D}esign of {I}ntegrated {C}ircuits and {S}ystems ({TCAD})},

  volume       = {28},

  number       = {12},

  pages        = {1870--1882},

  year         = {2009},

  }
• 

  Firew M. Siyoum. TLM-based Multi-core System Level Modeling and Simulation (TM2S). Master's thesis, Technische Universiteit Eindhoven, August 2009.

  The integration scale of semiconductor chips has been continuously soaring high throughout the years. Today, it is possible to integrate a complete system of IPs and communication networks on a tiny die area and form what is called a System-on-Chip (SoC). To cope with this growing complexity and time-to-market pressure, the SoC industry has accepted raising the abstraction level of system designs above RTL as an effective approach. ESL (Electronic System Level) refers to different system modeling techniques at a level of abstraction above RTL. As part of ESL, in recent years Transaction Level Modeling (TLM) is obtaining a huge attention in SoC design cycle, serving as a unique reference across different teams for three strategic activities: early software development, architecture analysis and functional verification. However, the name `transaction level' is still a vague term as it does not denote a single level of detail. Rather, TLM refers a continuum of abstraction levels that each vary in the amount of functional or temporal detail they express depending on the use case they are modeled for. Different researches have been made in the last few years to define these abstraction layers from different point of views such as granularity of time, functional abstraction, communication abstraction and use-cases. However the dust has not yet settled down. Issues on models interoperability, flexibility, efficiency and implementation details are not yet fully addressed due to the vastness of the topic. In this Master's thesis, an integrated TLM-based system level modeling approach for multi-core systems is devised which is mainly targeting streaming applications. The work begins with the specification of communication and computation refinement levels as well as definition of abstraction layers in system level modeling. Then, a library of communication APIs and models of components is prepared by reusing and modifying an existing framework called OCCN. Finally, a digital radio receiver streaming application and a high-level AMBA AHB bus model, are carried out to show the usage of the deviced methodology. The promising results obtained in simulation speed and model use-cases indicate that the approach lays down the foundation for an integrated system level modeling methodology which can be extended with new features and enhanced library into a complete tool.

  @mastersthesis{firew_2009,
  

  author       = {Firew M. Siyoum},

  title        = {{TLM}-based {M}ulti-core {S}ystem {L}evel {M}odeling and {S}imulation ({TM2S})},

  month        = aug,

  year         = {2009},

  school       = {Technische Universiteit Eindhoven},

  }